Computer Aided Synthesis and Design of Digital Systems
The goal of this course is to give the theoretical background and practical skills in the area of synthesis and design of the custom high-performance digital systems from high-level architectural synthesis to physical design stage. This course explores the methodologies for high-level synthesis and architecture-to-task optimization techniques for custom digital computing systems.
Topics include:
i) architecture classification of the digital computing systems,
ii) overview of recent hardware components for the custom digital systems (FPGA and CPLD), and hardware description languages (VHDL).
The methodology for high-level synthesis including formal selection of the optimum architecture in multi-parametric design space also is discussed in details. Case studies include the architectural synthesis of custom pipelined data-stream processor from specification to logic implementation. Students are expected to read selected papers from current research literature, learn one of hardware description languages (VHDL or Verilog) and perform a project using one of the commercial CAD system (Xilinx ISE or Altera “Quartus II”).
Course outline: EE-8208_Outline2011.pdf
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