WEEK |
LECTURE |
LABORATORY |
Handouts
|
| 1 |
Instruction Set principles: Instruction set architectures, Memory addressing modes, Operations and operands |
|
|
| 2 |
Classification of computer architectures: SISD, SIMD and MIMD architecture types.
Parallelism: Instruction-level (ILP), datalevel (DLP) and thread-level (TLP). |
Lab1: Introduction to DLX
simulator |
|
| 3 |
Pipelining: Basic pipeline and pipeline hazards: Structural hazard and Data hazards. Harvard architecture and Forwarding |
Lab 2: Studying DLX simulator |
|
| 4 |
Pipelining: Handle multi-cycle operations – multi-functional pipelined data-path Control
hazards and branch prediction mechanisms |
Lab 3: Evaluating DLX
Instruction set architecture. |
|
| 5 |
Instruction level parallelism (ILP):
Overcoming data hazards with Dynamic scheduling: Scoreboard and Tomasulo
approach |
Lab 4: Evaluating DLX
Instruction set architecture |
|
| 6 |
Instruction level parallelism (ILP):
Reducing branch penalties with Dynamic Hardware prediction |
Lab 5: Performance evaluation
of DLX based system |
|
| 7 |
Instruction level parallelism (ILP):
Multiple-issue processors |
Lab 6: Performance evaluation
of DLX based system |
|
| 8 |
Reading week |
|
|
| 9 |
Midterm test |
Lab 7: Performance evaluation
of DLX based system |
|
| 10 |
Instruction level parallelism (ILP):
Superscalar and VLIW architecture organizations |
Lab 8: Studying hazards using
DLX Simulator. |
|
| 11 |
Data-level parallelism (DLP): Vector processors and stream processors. |
Lab 9: Studying hazards using
DLX Simulator. |
|
| 12 |
Thread-level parallelism (TLP):
Multiprocessors: Centralized and
Shared-Memory architectures |
Lab 10: Performance of DLX
Architecture with pipelining |
|
| 13 |
Thread-level parallelism (TLP):
Synchronization, Multi-threading and simultaneous multi-threading |
Lab 11: Performance of DLX
Architecture with pipelining |
|
| 14 |
Reconfigurable multiprocessors:
FPGA. Reconfigurable architectures with static and dynamic (RTR) adaptation to the
task(s) algorithm and data structure |
Lab 12: Performance of DLX
Architecture with pipelining |
|
| 15 |
Final Examination |
|
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