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Computer Organization and Architecture
COE 608
B.Eng. 3rd Year

  Electrical, Computer and Biomedical Engineering

COE 608: Computer Organization and Architecture
 

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            TENTATIVE COURSE OUTLINE (also available in pdf format)

WEEK
                LECTURE
                      LABORATORY
01
 Computer Systems Technology:
Computer Organization, VHDL 		 
02
 Computer Performance:
Performance metrics and evaluation		 Lab1: Quartus-II-Altera FPGA Development
Environment and introduction to VHDL
Lab1: Submission
03
 Instruction set Design:
Instruction representation
Arithmetic and Logic Operations		 Lab 2: Program counter and Register set design:
VHDL code design and Simulation
04
 Instruction set Design:
Addressing modes and Branching		 Lab 2: Submission
Lab 3a: 32-bit ALU design
05
 Arithmetic for computers:
Integer arithmetic operations
Logical operations 		Lab 3a: Submission
Lab 3b: 8-bit ALU Implementation
06
 Arithmetic for computers:
ALU Design and Implementation		 Lab 3b: Submission
Lab 4a: Data Memory Module
SW
 Study Week
07
 Midterm Exam Lab 4a: Submission
Lab 4b: CPU Datapath design
08
 Datapath:
Register transfer, Control Unit Design Single- and Multi-cycle Datapath Design		 Lab 4b: CPU Datapath design and simulation
09
 Datapath and Control
Single- and Multi-cycle Datapath Design		 Lab 4b: Submission
Lab 5: CPU Control Unit design
10
 CPU Control Unit
ASM Charts and Control unit Design
and Implementation		 Lab 5: CPU Control Unit design
11
 Pipelining: Basic Concepts Lab 5: Submission
Lab 6: Integration of CPU
12
 Pipelining:
Data Hazards and Branch Hazards
Stalls and Forwarding		 Lab 6: Integration and simulation of CPU
Overall CPU Project Demonstration
13
 Catching up and review Lab 6: Submission
Overall CPU Project Bonus Demonstration

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