Design and FPGA Implementation of 2D-NoC based System-on-Chip

2018 COE Engineering Design Project (GK03)

Faculty Lab Coordinator

Gul Khan

Topic Category

FPGA / Reconfigurable Computing


NoC (Network-on-Chip) interconnects have emerged to address performance limitations and overhead of bus-based Multi-Processor System-on-Chip (SoC) architectures. NoC replaces the buses with routers and links or channels, where data packets communicate simultaneously using wormhole communication via channels between various on-chip cores. Generally, a physical link supports several virtual channels that are multiplexed across the physical channel. By allowing packet-based messages to share a physical channel, messages can make progress rather than remain blocked, leading to high performance NoCs. NoC router is the main IP core that facilitate the implementation of an NoC based SoC for various high-performance applications.


Investigate and develop an NoC router core (IP) for NoC based System-on-Chip (SoC). NoC verification by implementing a typical high-performance application.

Partial Specifications

1. Study of NoC systems and Investigation of the design of 2D-NoC router.
2. Selection of a typical high-performance application for multi-core system.
3. Design and implement the NoC router IP core RTL using VHDL or Verilog.
4. Verify the router core by prototyping a Multi-core NoC on a FPGA by using soft
CPU cores and accelerator IPs for a typical application.

Suggested Approach

1. Select and study an Altera Cyclone IV/V or a comparable Xilinx FPGA board for developing the NoC system.
2. Study NoC architecture and Mesh based NoC.
3. Explore various on-chip routing techniques specifically wormhole routing.
4. Investigation of the architecture and specification of various NoC routers.
5. RTL design and Implement (preferably Verilog based) NoC router for a well known NoC topology such as 2D-mesh.
6. Implement the NoC based SoC and map a suitable application.

Group Responsibilities

1. Study suitable FPGA based (Cyclone) embedded platforms for some typical NoC applications. 2. Survey the development being carried out by different groups working on NoC router IPs. 3. Develop a detailed specification of an NoC router. 4. Design/develop the NoC router by using VHDL or Verilog, and prototype it on the FPGA platform. 5. Verify the NoC router and utilize it to prototype NoC based SoC. 6. Implement a suitable application my mapping it to the designed SoC.

Student A Responsibilities

1. Study a couple FPGA-based embedded platforms for NoC implementation. 2. Investigate and study various NoC router architectures for implementation. 3. Design and write the NoC router specification (using System Verilog and/or SystemC) suitable for NoC systems. 4. Develop the NoC router design by working with Student B. 5. Assist Student B and C and manage the overall project design and implementation.

Student B Responsibilities

1. Investigate some candidate Nios-II/microblaze/ARM-A9 processor-based FPGA or other platforms. 2. Improve the router specification (prepared by student A) and develop the NoC router. 3. Overall design of an NoC system by employing the NoC router for a typical NoC application with the help of student A and C. 4. Assist Student A and C to manage the overall project design and implementation.

Student C Responsibilities

1. Study some multi-core embedded applications suitable for NoC based SoC implementation. 2. Employ the simple NoC router to establish communication between routers. 3. Design and establish communication between a CPU, accelerator and memory IP cores. 4. Implement the NoC system by employing the NoC router with the help of student A and B. 5. Assist Student A and B to manage the overall project design and implementation.

Course Co-requisites

COE718, COE838


GK03: Design and FPGA Implementation of 2D-NoC based System-on-Chip | Gul Khan | Monday August 27th 2018 at 10:14 PM