Dr. Andy G. Ye

Associate Professor | Department of Electrical, Computer, and Biomedical Engineering | Toronto Metropolitan University

About Me

Andy Gean Ye received his Ph.D. degree in Computer Engineering from the University of Toronto in 2004. He also received his B.A.Sc. and M.A.Sc. degrees from the same university in 1996 and 1999, respectively. In 1996, he graduated first in class in the Engineering Science program.

Email: agye@torontomu.ca | Office: ENG319

Research Interests

My research group currently has positions open for graduate studies at the M.A.Sc. and Ph.D. levels. We seek capable, hardworking individuals interested in further developing digital hardware design skills in neuromorphic computing and FPGA architectures. The candidate should have a B.A.Sc./M.A.Sc. degree in Electrical Engineering, Computer Engineering or Computer Science.

Current Graduate Students

Former Graduate Students

Publications

Google Scholar

    Journal Papers and Refereed Publications in Major Computer Engineering Conferences

  1. "Learning-based regression for rapid design-space exploration in FPGA architectures."
    Mousa Al-Qawasmi and Andy Ye (2026). Elsevier Results in Engineering, Vol. 31, September 2026, pp. 111326.
  2. "Measuring the Power Constrained Performance of FPGA Architectures in ASAP5 GAA NWFET."
    Andy Ye (2025). Proceedings of the 2025 IEEE International Conference on Field Programmable Technology (ICFPT), Shanghai, China, December 2025, pp 64-72. (Acceptance Rate: 24.7%) (Please email me to request for artifacts related to this paper.)
  3. "Scaling the Area of Synthesizable FPGA Tiles Across Semiconductor Process Nodes."
    Mousa Al-Qawasmi and Andy Ye (2025). MDPI Microelectronics, Vol. 1, No. 2, November 2025.
  4. "Regression-based Approach Towards Estimating the Area, Delay and Leakage Power of Synthesizable FPGA Tiles."
    Mousa Al-Qawasmi and Andy Ye (2024). Proceedings of the 2024 IEEE International Conference on Field Programmable Technology (ICFPT), Sydney, Australia, December 2024, pp 1-10. (Acceptance Rate: 27.5%)
  5. "Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm."
    Sajjad Rostami Sani and Andy Ye (2024). ACM Transactions on Reconfigurable Technology and Systems, Vol. 17, No. 1, February 2024, pp 1-29.
  6. "The Effect of Gate Voltage Boosting on the Power Efficiency of Multi-Context FPGAs."
    Anas Razzaq, Sajjad Rostami-Sani, and Andy Ye (2022). Elsevier Integration, the VLSI Journal, Vol. 86, No. 9, September 2022, pp. 30-43.
  7. "Measuring the Effect of Track Count and Wire Segment Length on the Layout Area of Switch Blocks for Tile-Based FPGAs."
    Sajjad Rostami-Sani and Andy Ye (2022). Elsevier Microprocessors and Microsystems, Vol 92, No. 7, July 2022.
  8. "Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm."
    Sajjad Rostami-Sani, Anas Razzaq, and Andy Ye (2022). Proceedings of the 2022 IEEE 30th International Symposium on Field-Programmable Custom Computing Machines, New York City, NY, May 2022, pp 1-9. (Acceptance Rate: 17.5%)
  9. "Designing Efficient FPGA Tiles for Power-Constrained Ultra-Low-Power Applications."
    Anas Razzaq, Sajjad Rostami-Sani, and Andy Ye (2021). Elsevier Integration, the VLSI Journal, Vol. 78, No. 5, May 2021, pp. 124-134.
  10. "Static Power Model for CMOS and FPGA Circuits."
    Anas Razzaq and Andy Ye (2021). IET Computers & Digital Techniques, Vol. 15, No. 4, April 2021, pp. 263-278.
  11. "Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology."
    Sajjad Rostami-Sani, Farheen Khan, and Andy Ye (2020). Proceedings of the 2020 IEEE 30th International Conference on Field Programmable Logic and Applications, Gothenburg, Sweden, August 2020, pp. 214-219. (Short Paper, Acceptance Rate: 32% Long and Short Paper Combined)
  12. "An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures."
    Farheen Khan and Andy Ye (2018). ACM Transactions on Reconfigurable Technology and Systems, Vol. 11, No. 1, March 2018, pp. 1-23.
  13. "A Study on the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area."
    Farheen Khan and Andy Ye (2017). Elsvier Microprocessors and Microsystems, Vol. 52, No. 7, July 2017, pp. 287-298.
  14. "An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures."
    Farheen Khan and Andy Ye (2016). Proceedings of the 2016 26th International Conference on Field Programmable Logic and Applications, Lausanne, Switzerland, September 2016, pp. 1-11. (Best Paper Award, Acceptance Rate: 21%)
  15. "Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area."
    Farheen Khan and Andy Ye (2015). Proceedings of the 2015 23rd IEEE International Syposium on Field-Programmable Custom Computing Machines, Vancouver, British Columbia, May 2015, pp. 223-226. (Short Paper, Acceptance Rate: 38.9% Long and Short Paper Combined)
  16. "Design Techniques for Decision Feedback Equalisation of Multi-giga-bit-per-second Serial Data Links: a State-of-the-art Review."
    Fei Yuan, Alaa R. Abdullah and Andy Ye (2014). IET Circuits, Devices and Systems, Vol. 8, No. 2, April 2014, pp. 118-130.
  17. "New 2-D Eye-Opening Monitor for Gb/s Serial Links."
    Alaa R. Abdullah, Fei Yuan, and Andy Ye (2014). IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 6, June 2014, pp. 1209-1218.
  18. "Analysis and Architecture Design of Scalable Fractional Motion Estimation for H.264 Encoding."
    Jasmina Vasiljevic and Andy Ye (2012). Elsevier Integration, the VLSI Journal, Vol. 45, No. 4, April 2012, pp. 427-438.
  19. "Utilizing Multi-Bit Connections to Improve the Area Efficiency of Unidirectional Routing Resources for Routing Multi-Bit Signals on FPGAs."
    Omesh Mutukuda, Andy Ye, and Gul Khan (2012). Elsevier Microprocessors and Microsystems - Embedded Hardware Design, Vol. 36, No. 3, March 2012, pp. 167-175.
  20. "Measuring the Power Efficiency of Subthreshold FPGAs for Implementing Portable Biomedical Applications."
    Shahin Sanayei Lotfabadi, Andy Ye, and Sridhar Krishnan (2012). Elsevier Microprocessors and Microsystems - Embedded Hardware Design, Vol. 36, No. 3, March 2012, pp. 151-158.
  21. "The Effect of Scaling on the Area and Performance of the H.264/AVC Full-Search Fractional Motion Estimation Algorithm on FPGAs."
    Jasmina Vasiljevic and Andy Ye (2012). IET Computers and Digital Techniques, Vol. 6, No. 2, February 2012, pp. 95-104.
  22. "VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity and Process Scaling."
    J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. Fang, K. Kent, and J. Rose (2011). ACM Transactions on Reconfigurable Technology and Systems, Vol. 4, No. 4, December 2011, pp. 32-54.
  23. "The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources."
    Ping Chen and Andy Ye (2011). IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 2, February 2011, pp. 283-294.
  24. "The Effect of Multi-bit Based Connections on the Area Efficiency of FPGAs Utilizing Unidirectional Routing Resources."
    O. Mutukuda, A. Ye, and G. Khan (2010). Proceedings of the 2010 IEEE International Conference on Field-Programmable Technology, Tsinghua University, Beijing, China, December 2010, pp. 216-223. (Acceptance Rate: 22.3%)
  25. "Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs."
    Andy Ye (2010). IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, No. 1, January 2010, pp. 95-107.
  26. "VPR 5.0: FPGA CAD and Architecture Exploration with Single-Driver Routing, Heterogeneity and Process Scaling."
    Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, and Jonathan Rose (2009). Proceedings of the 2009 ACM/SIGDA 17th International Symposium on Field-Programmable Gate Arrays, Monterey, California, February 2009, pp. 133-142.(Acceptance Rate: 26.1%)
  27. "A Scalable Computing and Memory Architecture for Variable Block Size Motion Estimation on Field-Programmable Gate Arrays."
    Theepan Moorthy and Andy Ye (2008). Proceedings of the 2008 IEEE 18th International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, September 2008, pp. 83-88.(Acceptance Rate: 28%)
  28. "The Effect of Sparse Switch Patterns on the Area Efficiency of Multi-Bit Routing Resources in Field-Programmable Gate Arrays."
    P. Chen and A. Ye (2008). Proceedings of the 2008 IEEE 18th International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, September 2008, pp. 427-430. (Short Paper, Acceptance Rate: 55% Long and Short Paper Combined).
  29. "Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits."
    Andy Ye and Jonathan Rose (2006). IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 5, May 2006, pp. 462-473.
  30. "Measuring and Utilising the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks."
    Andy Ye and Jonathan Rose (2006). IEE Proceedings - Computers and Digital Techniques, Vol. 153, No. 3, May 2006, pp. 146-156.
  31. "Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks."
    Andy Ye and Jonathan Rose (2005). Proceedings of the 2005 IEEE 15th International Conference on Field Programmable Logic and Applications, Tampere, Finland, August 2005, pp. 159-166. (Acceptance Rate: 29.3%)
  32. "Using Bus-Based Connections to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits."
    Andy Ye and Jonathan Rose (2005). Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2005, pp. 3-13. (Acceptance Rate: 24%)
  33. "Using Multi-Bit Logic Blocks and Automated Packing to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits."
    Andy Ye and Jonathan Rose (2004). Proceedings of the 2004 IEEE Third International Conference on Field-Programmable Technology, Brisbane, Australia, December 2004, pp. 129-136. (Acceptance Rate: 27.9%)
  34. "Architecture of Datapath-Oriented Coarse-Grain Logic and Routing for FPGAs."
    Andy Ye, Jonathan Rose, and David Lewis (2003). Proceedings of the 25th IEEE Custom Integrated Circuits Conference 2003, San Jose, CA, September 2003, pp. 61-64. (Acceptance Rate: 38.7%)
  35. "Synthesizing Datapath Circuits for FPGAs with Emphasis on Area Minimization."
    Andy Ye, Jonathan Rose, and David Lewis (2002). Proceedings of the 2002 IEEE First International Conference on Field-Programmable Technology, Hong Kong, December 2002, pp. 219-226. (Acceptance Rate: 31.6%)
  36. "Procedural Texture Mapping on FPGAs."
    Andy Ye and David M. Lewis (1999). Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 1999, pp. 112-120. (Acceptance Rate: 21%) (Colour Version [PDF])

    37. Other Refereed Publications in Conferences and Workshops

  37. "Measuring the Minimum Power Requirement of FPGA Architectural Specifications."
    Andy Ye and Anas Razzaq (2025). Proceeding of the 2025 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside CA, February 2025, pp 180. (Poster, Acceptance Rate: 52.4% Full Paper, Short Paper and Poster Combined)
  38. "Estimating Post-Synthesis Area, Delay, and Leakage Power of Standard Cell Based FPGA Tiles."
    Mousa Al-Qawasmi and Andy Ye (2023). Proceedings of the 2023 Annual IEEE Canadian Conference on Electrical and Computer Engineering, Regina, SK, September 2023, pp 117-123.
  39. "An Investigation of the Accuracy of the VPR and COFFE Area Models in Predicting the Layout Area of FPGA Lookup Tables."
    Mousa Al-Qawasmi and Andy Ye (2020). Proceedings of the IEEE SoutheastCon 2020, Raleigh, NC, March 2020, pp 1-9.
  40. "A Scene-Based Augmented Reality Framework for Exhibits."
    Julien Li-Chee-Ming, Zheng Wu, Randy Tan, Ryan Tan, Naimul Mefraz Khan, Andy Ye and Ling Guan (2019). Proceedings of the 16th International Conference on Image Analysis and Recognition, Waterloo, Ontario, August 2019, pp 287-296.
  41. "Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors."
    Andy Ye and Karthik Ganesan (2017). Proceeding of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey CA, February 2017, pp 285. (Poster, Acceptance Rate: 58.4% Full Paper, Short Paper and Poster Combined)
  42. "An Empirical Analysis of the Fidelity of VPR Area Models."
    Farheen Khan and Andy Ye (2016). Proceedings of 2016 IEEE 24th International Symposium on Field-Programmable Custom Computing Machines, Washington DC, May 2016, pp 138. (Poster, Acceptance Rate: 40% Long Paper, Short Papr and Poster combined)
  43. "Hardware-Software Analysis of Pole Model Features."
    Hamid Asefi, Behnaz Ghoraani, Andy Ye, and Sri Krishnan (2011). Proceedings of the 2011 IEEE 24th Canadian Conference on Electrical and Computer Engineering, Niagara Falls, Ontario, May 2011, pp. 1288-1291.
  44. "Audio Scene Analysis using Parametric Signal Features."
    Hamid Asefi, Behnaz Ghoraani,Andy Ye, and Sri Krishnan (2011). Proceedings of the 2011 IEEE 24th Canadian Conference on Electrical and Computer Engineering, Niagara Falls, Ontario, May 2011, pp. 922-925.
  45. "A Study on the Scalability of the H.264/AVC Fractional Motion Estimation Algorithm on FPGAs."
    Jasmina Vasiljevic and Andy Ye (2010). Proceedings of the 2010 IEEE 18th Symposium on Field Programmable Custom Computing Machines, Charlotte, North Carolina, May 2010, pp. 283. (Poster)
  46. "A Scalability Study of Fractional Motion Estimation for H.264 Encoding."
    Jasmina Vasiljevic and Andy Ye (2010). Proceedings of the 2010 IEEE 18th Canadian Conference on Electrical and Computer Engineering, Calgary, Alberta, May 2010, pp. 1-5.
  47. "A Scalable Architecture for Variable Block Size Motion Estimation on Field-Programmable Gate Arrays."
    Theepan Moorthy and Andy Ye (2008). Proceedings of the 2008 IEEE 16th Canadian Conference on Electrical and Computer Engineering, Niagara Falls, Canada, May 2008, pp. 1303-1308.
  48. "Procedural Texture Mapping Using the Transmogrifier-2."
    Andy Ye and David M. Lewis (1999). Micronet Conference, Ottawa, Ontario, 1999.
  49. "Procedural Texture Mapping Using Transmogrifier-2: An Initial Study."
    Andy Ye and David M. Lewis (1997). University of Toronto Field Programmable Gate Array Research Retreat, Toronto, Ontario, June 1997.

    50. Invited Talks

  50. "Minimum-Area IIB - How to Minimize the Area of a Logic Cluster without Losing any Functionality?."
    Andy Ye (2010). University of British Columbia Cascadia Workshop, Vancouver, British Columbia, August 13, 2010. [PDF]
  51. "Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs."
    Andy Ye (2009). University of Toronto FPGA Research Seminar, Toronto, Ontario, October 15, 2009.
  52. "FPGA Routing Architectures for Datapath Circuits."
    Phoebe Ping Chen and Andy Ye (2008). University of Toronto FPGA Research Seminar, Toronto, Ontario, May 15, 2008.
  53. "FPGA Hardware Acceleration for H.264 Motion Estimation."
    Theepan Moorthy and Andy Ye (2008). University of Toronto FPGA Research Seminar, Toronto, Ontario, April 17, 2008.
  54. "Using Bus-Based Connections to Improve FPGA Density for Implementing Datapath Circuits."
    A. Ye and J. Rose (2005). Connections 2005 Research Review, University of Toronto, Toronto, Ontario, June 2005.
  55. "Field-programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits."
    Andy Ye, Jonathan Rose, and David M. Lewis (2004). Xilinx Inc., Toronto, Ontario, February 27, 2004. [PowerPoint]
  56. "Architecture of Datapath-Oriented Coarse-Grain Logic and Routing for FPGAs."
    Andy Ye, Jonathan Rose, and David M. Lewis (2003). Altera Corp., Toronto, Ontario, October 9, 2003. [PowerPoint]
  57. "Architecture of Datapath-Oriented Coarse-Grain Logic and Routing for FPGAs."
    Andy Ye, Jonathan Rose, and David M. Lewis (2003). Xilinx Inc., Toronto, Ontario, July 2003. [PowerPoint]
  58. "Synthesizing Datapath Circuits for FPGAs with Emphasis on Area Minimization."
    Andy Ye, David M. Lewis, and Jonathan Rose (2002). Xilinx Inc., Toronto, Ontario, July 2002. [PowerPoint]
  59. "Procedural Texture Mapping Using FPGAs."
    Andy Ye and David M. Lewis (1997). ATI Technologies Inc., Thornhill, Ontario, August 1997. [PDF]

    60. Thesis and Technical Reports

  60. "Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits."
    Andy Ye (supervised by Jonathan Rose and David Lewis) (2004). Ph.D. Thesis, Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, November 2004. [PDF]
  61. "Ph.D. Progress Report --- Report #3."
    Andy Ye (2003). Ph.D. Thesis Monitoring Report, Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, May 2003. [PDF]
  62. "Ph.D. Progress Report --- Report #2."
    Andy Ye (2002). Ph.D. Thesis Monitoring Report, Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, May 2002. [PDF]
  63. "Ph.D. Progress Report --- Report #1."
    Andy Ye (2001). Ph.D. Thesis Monitoring Report, Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, August 2001. [PDF]
  64. "Ph.D. Thesis Proposal: Routing Architecture and Place and Route Tools for DP-FPGA."
    Andy Ye and David M. Lewis (2000). Ph.D. Thesis Proposal, Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, July 2000. [PDF]
  65. "Procedural Texture Mapping on FPGAs."
    Andy Ye (supervised by David M. Lewis) (1999). M.A.Sc. Thesis, Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 1999. [PDF]
  66. "Analyzing and Designing Linear Quadratic Gaussian Controllers for a Dual Link Flexible System."
    Andy Ye(supervised by Raymond H. Kwong) (1996). B.A.Sc. Thesis, Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 1996.