Course Outline (W2023)
ELE863: VLSI Circuits for Data Communications
|Instructor(s)||Dr. Fei Yuan [Coordinator]|
Office: ENG 433
Phone: (416) 979-5000 x 556100
Office Hours: Mon. 9-10 am via ZOOM
|Calendar Description||An advanced course on design of VLSI circuits for data communications over wire channels. The theoretical component consists of: switching noise and grounding of mixed analog-digital circuits, modeling of wire channels, clock generation and distribution, power distribution on chip, ESD protection, channel equalization, clock and data recovery. The laboratory component consists of design of clock and data recovery circuits using state-of-the-art CMOS technology and CAD tools.
|Prerequisites||ELE 727 or ELE 734|
- ELE 863 Lecture Notes from Dr. Fei Yuan (available from D2L).
- Laboratory manual: ELE 863 Laboratory Manual (available from D2L).
- W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.
- B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003
- H. Johnson and M. Graham, High-speed digital design - A handbook of black magic, Prentice-Hall, 1993.
- F. Yuan, CMOS Current-Mode Circuits for Data Communications. Springer, 2006.
- Stojanovic, Channel-limited high-speed links: modeling, analysis and design, PhD Dissertation, Stanford University, 2004.
- Published peer-reviewed scientific papers in scientific journals and conference proceedings.
|Learning Objectives (Indicators) |
At the end of this course, the successful student will be able to:
- Improve their capabilities of using the technical knowledge of VLSI circuits to design a transceiver for data communications. (4b)
- Utilize computer-aided design tools for integrated
circuit design to iteratively design a transceiver for data communications over wire channels. (4c)
- Proficiency in use of computer-aided design tools from Cadence Design Systems for integrated circuit design to
design and analyze a transceiver for data communications over wire channels. (5a)
- Write professionally prepared laboratory reports. Laboratory reports are evaluated on their correctness, completeness, English, and quality of graphics. (7a), (7c)
NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB).
3.0 hours of lecture per week for 13 weeks
2.0 hours of lab per week for 12 weeks
0.0 hours of tutorial per week for 12 weeks
|Teaching Assistants||Ian Perczak. Email : firstname.lastname@example.org|
|Midterm Exam|| 30 %|
|Final Exam|| 30 %|
|Lab Projects|| 40 %|
Note: In order for a student to pass a course, a minimum overall course mark of 50% must be obtained. In addition, for courses that have both "Theory and Laboratory" components, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section above for details on the Theory and Laboratory components (if applicable).
|Examinations||1. 3-hour closed-book midterm exam during regular lecture time on Feb. 22.|
2. 3-hour closed-book final exam during university exam period with date/time set by the university. Only course materials covered AFTER the midterm exam will be tested.
|Other Evaluation Information||None|
Distributed lecture notes
Module 1 - Modeling of wire channels
1) Components of wire channels
2) Scaling of wire channels
3) Resistance of wire channels
4) Capacitance of wire channels
5) Inductance of wire channels
6) Modeling of wire channels at low, intermediate, and high frequencies
7) Transmission-line effect (perfect/under/over termination)
8) Termination schemes
Distributed lecture notes
Module 2 - Electrical signaling
1) Single-ended signaling
2) Fully differential signaling
3) Pseudo-differential signaling
4) Voltage-mode incremental signaling
5) Current-mode signaling
6) Current-mode incremental signaling
Distributed lecture notes
Module 3 - Fundamentals of serial links
1) Data encoding for serial links
2) Data modulation for serial links
3) Eye diagrams
4) Inter-symbol interference (ISI)
5) Bit-error rate
6) Test of serial links
Distributed lecture notes
Module 4 - Pre-emphasis
1) Channel equalization
2) Pre-emphasis strategies
3) Basic idea of pre-emphasis
4) Pre-emphasis algorithms
5) Pre-emphasis algorithms : A zero/pole perspective
6) Pre-emphasis algorithms : A frequency response perspective
7) Pre-emphasis waveforms
8) Implementation of pre-emphasis FIR filters
9) Advantages of pre-emphasis
10) Limitations of pre-emphasis
Distributed lecture notes
Module 5 - Continuous-time linear equalization
1) Channel impairments
2) Channel equalization
3) Continuous-time linear equalization
4) Continuous-time linear equalization - Source degeneration
5) Continuous-time linear equalization - Negative capacitors
6) Continuous-time linear equalization - Inductor shunt-peaking
7) Continuous-time linear equalization - Complete design
Mid-term examination during normal lecture time on Feb. 22.
Distributed lecture notes
Module 6 – Phase/frequency-locked loop
1) Voltage-controlled ring oscillators
3) Spectrum (phase noise) of oscillators
4) Phase detectors
5) Charge pumps
6) Loop filters
7) Loop dynamics of type-1 phase-locked loops
8) Loop dynamics of type-2 phase-locked loops
9) Phase noise of phase-locked loops
10) All-digital phase-locked loops
- TDC-based ADPLL
- Delay line TDC
- Delay-locked loops
- Vernier TDC
- Cyclic Vernier TDC
- Digital phase interpolation
- Digital loop filters (FIR, IIR filters)
- Digital controlled oscillators (DCOs)
11) Frequency synthesizers
- Injection-locked frequency dividers
- DFF-based frequency dividers
- Frequency difference detectors
- Frequency-locking and phase-locking in frequency synthesizers
Distributed lecture notes
Module 7 - Decision feedback equalization (DFE)
7.1 Decision feedback equalization
1) Postcursor-induced ISI
2) Principle of DFE
3) Configuration of DFE
4) Characteristics of DFE
5) Challenges of DFE
6) DFE blocks
7.2 Adaptive decision feedback equalization
1) Classification of DFE
2) Data-state (DS) DFE
3) Data-transit (DT) DFE
4) Weighted DS-DFE and DT-DFE
5) Adaptive DFE
6) Least-mean-square (LMS) adaptive DFE algorithm
7) Sign-sign (S$^2$) LMS adaptive DFE algorithm
8) SS-LMS implementation
9) Error detection unit for adaptive DS-DFE
10) Reference voltages
11) Error detection unit for adaptive DT-DFE
12) Charge pumps and loop filters
Distributed lecture notes
Module 8 - Clock and data recovery
1) Clock recovery
2) Frequency drift of receiver PLL
3) Direct coupling and AC coupling
4) Data encoding
5) Classification of clock recovery
6) Clock recovery using phase tracking
7) Clock recovery using phase picking
8) Clock recovery using phase interpolation
Wire channels. Report due : Sunday mid-night of Week 2 if your lab is in Week 1 and Sunday mid-night of Week 3 if your lab is in Week 2.
Pre-emphasis. Report due : Sunday mid-night of week 4 if your lab is in Week 3 and Sunday mid-night of Week 5 if your lab is in Week 4.
Continuous-time linear equalizer/Phase-locked loop. CTLE report due : Sunday mid-night of week 6 if your lab is in Week 5 and Sunday mid-night of Week 7 if your lab is in Week 6.
Phase-locked loop. PLL report due : Sunday mid-night of week 8 if your lab is in Weeks 5/7 and Sunday mid-night of Week 9 if your lab is in Weeks 6/8.
Decision feedback equalizer. Report due : Sunday mid-night of week 10 if your lab is in Week 9 and Sunday mid-night of Week 11 if your lab is in week 10.
Clock and data recovery. Report due : Sunday mid-night of week 12 if your lab is in Week 11 and Sunday mid-night of Week 13 if your lab is in Week 12.
Policies & Important Information:
Students are reminded that they are required to adhere to all relevant university policies found in their online course shell in D2L and/or on the Senate website
- In accordance with the Policy on TMU Student E-mail Accounts (Policy 157), Toronto Metropolitan University (TMU) requires that any electronic communication by students to TMU faculty or staff be sent from their official university email account;
- Any changes in the course outline, test dates, marking or evaluation will be discussed in class prior to being implemented;
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Information will be provided prior to the exam date by your instructor who may provide an opportunity to test your set-up or provide additional information about online proctoring. Since videos of you and your environment will be recorded while writing the exam, please consider preparing the background (room / walls) so that personal details are not visible, or move to a room that you are comfortable showing on camera.
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Suspicions of academic misconduct may be referred to the Academic Integrity Office (AIO). Students who are found to have committed academic misconduct will have a Disciplinary Notation (DN) placed on their academic record (not on their transcript) and will normally be assigned one or more of the following penalties:
- A grade reduction for the work, ranging up to an including a zero on the work (minimum penalty for graduate work is a zero on the work);
- A grade reduction in the course greater than a zero on the work. (Note that this penalty can only be applied to course components worth 10% or less, and any additional penalty cannot exceed 10% of the final course grade. Students must be given prior notice that such a penalty will be assigned (e.g. in the course outline or on the assignment handout);
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For more detailed information on these issues, please refer to the Academic Integrity policy(https://www.torontomu.ca/senate/policies/pol60.pdf) and to the Academic Integrity Office website (https://www.torontomu.ca/academicintegrity).
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Please note that the Provost/Vice President Academic and Deans approved a COVID-19 statement for Fall 2022 related to academic consideration. This statement will be built into the Online Academic Consideration System and will also be on the Senate website (www.torontomu.ca/senate) in time for the Fall term:
Policy 167: Academic Consideration for Fall 2022 due to COVID-19: Students who miss an assessment due to cold or flu-like symptoms, or due to self-isolation, are required to provide a health certificate. All absences must follow Senate Policy 167: Academic Consideration.
Also NOTE: Policy 167: Academic Consideration does allow for a once per term academic consideration request without supporting documentation if the absence is less than 3 days in duration and is not for a final exam/final assessment. If the absence is more than 3 days in duration and/or is for a final exam/final assessment, documentation is required. For more information please see Senate Policy 167: Academic Consideration.
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- TMU COVID-19 Vaccination Policy.
- If taking a remote course, familiarize yourself with the tools you will need to use for remote learning. The Remote Learning guide for students includes guides to completing quizzes or exams in D2L Brightspace, with or without Respondus LockDown Browser and Monitor, using D2L Brightspace, joining online meetings or lectures, and collaborating with the Google Suite.
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