ELE863-W2026-CourseOutline.pdf

Week	Hours	Chapters / Section	Topic, description
1-2			Module 1 - Modeling of wire channels 1) Components of wire channels 2) Scaling of wire channels 3) Resistance of wire channels 4) Capacitance of wire channels 5) Inductance of wire channels 6) Modeling of wire channels at low, intermediate, and high frequencies 7) Transmission-line effect 8) Termination schemes
3			Module 2 - Electrical signaling 1) Single-ended signaling 2) Fully differential signaling 3) Pseudo-differential signaling 4) Voltage-mode incremental signaling 5) Current-mode signaling 6) Current-mode incremental signaling
3			Module 3 - Fundamentals of serial links 1) Data encoding for serial links 2) Data modulation for serial links 3) Eye diagrams 4) Inter-symbol interference 5) Bit-error rate 6) Test of serial links
4			Module 4 - Pre-emphasis 1) Channel equalization 2) Pre-emphasis strategies 3) Basic idea of pre-emphasis 4) Pre-emphasis algorithms 5) Pre-emphasis algorithms : A zero/pole perspective 6) Pre-emphasis algorithms : A frequency response perspective 7) Pre-emphasis waveforms 8) Implementation of pre-emphasis FIR filters 9) Advantages of pre-emphasis 10) Limitations of pre-emphasis
5			Module 5 - Continuous-time linear equalization 1) Channel impairments 2) Channel equalization 3) Continuous-time linear equalization 4) Continuous-time linear equalization - Source degeneration 5) Continuous-time linear equalization - Negative capacitors 6) Continuous-time linear equalization - Inductor shunt-peaking 7) Continuous-time linear equalization - Complete design
6			Mid-term examination during normal lecture time on Feb. 22.
7-9			Module 6 Phase/frequency-locked loop 1) Voltage-controlled ring oscillators 2) Noise 3) Spectrum (phase noise) of oscillators 4) Phase detectors 5) Charge pumps 6) Loop filters 7) Loop dynamics of type-1 phase-locked loops 8) Loop dynamics of type-2 phase-locked loops 9) Phase noise of phase-locked loops 10) All-digital phase-locked loops - TDC-based ADPLL - Delay line TDC - Delay-locked loops - Vernier TDC - Cyclic Vernier TDC - Digital phase interpolation - Digital loop filters (FIR, IIR filters) - Digital controlled oscillators (DCOs) 11) Frequency synthesizers - Injection-locked frequency dividers - DFF-based frequency dividers - Frequency difference detectors - Frequency-locking and phase-locking in frequency synthesizers
10-11			Module 7 - Decision feedback equalization (DFE) 7.1 Decision feedback equalization 1) Postcursor-induced ISI 2) Principle of DFE 3) Configuration of DFE 4) Characteristics of DFE 5) Challenges of DFE 6) DFE blocks 7.2 Adaptive decision feedback equalization 1) Classification of DFE 2) Data-state (DS) DFE 3) Data-transit (DT) DFE 4) Weighted DS-DFE and DT-DFE 5) Adaptive DFE 6) Least-mean-square (LMS) adaptive DFE algorithm 7) Sign-sign (S$^2$) LMS adaptive DFE algorithm 8) SS-LMS implementation 9) Error detection unit for adaptive DS-DFE 10) Reference voltages 11) Error detection unit for adaptive DT-DFE 12) Charge pumps and loop filters
12-13			Module 8 - Clock and data recovery 1) Clock recovery 2) Frequency drift of receiver PLL 3) Direct coupling and AC coupling 4) Data encoding 5) Classification of clock recovery 6) Clock recovery using phase tracking 7) Clock recovery using phase picking 8) Clock recovery using phase interpolation

Week

Hours

Chapters /
Section

Topic, description

1-2

Module 1 - Modeling of wire channels
   1) Components of wire channels
   2) Scaling of wire channels
   3) Resistance of wire channels
   4) Capacitance of wire channels
   5) Inductance of wire channels
   6) Modeling of wire channels at low, intermediate, and high frequencies
   7) Transmission-line effect
   8) Termination schemes

Module 2 - Electrical signaling
   1) Single-ended signaling
   2) Fully differential signaling
   3) Pseudo-differential signaling
   4) Voltage-mode incremental signaling
   5) Current-mode signaling
   6) Current-mode incremental signaling

Module 3 - Fundamentals of serial links
   1) Data encoding for serial links
   2) Data modulation for serial links
   3) Eye diagrams
   4) Inter-symbol interference
   5) Bit-error rate
   6) Test of serial links

Module 4 - Pre-emphasis
    1) Channel equalization
    2) Pre-emphasis strategies
    3) Basic idea of pre-emphasis
    4) Pre-emphasis algorithms
    5) Pre-emphasis algorithms : A zero/pole perspective
    6) Pre-emphasis algorithms : A frequency response perspective
    7) Pre-emphasis waveforms
    8) Implementation of pre-emphasis FIR filters
    9) Advantages of pre-emphasis
    10) Limitations of pre-emphasis

Module 5 - Continuous-time linear equalization
    1) Channel impairments
    2) Channel equalization
    3) Continuous-time linear equalization
    4) Continuous-time linear equalization - Source degeneration
    5) Continuous-time linear equalization - Negative capacitors
    6) Continuous-time linear equalization - Inductor shunt-peaking
    7) Continuous-time linear equalization - Complete design

Mid-term examination during normal lecture time on Feb. 22.

7-9

Module 6 Phase/frequency-locked loop
   1) Voltage-controlled ring oscillators
   2) Noise
   3) Spectrum (phase noise) of oscillators
   4) Phase detectors
   5) Charge pumps
   6) Loop filters
   7) Loop dynamics of type-1 phase-locked loops
   8) Loop dynamics of type-2 phase-locked loops
   9) Phase noise of phase-locked loops
   10) All-digital phase-locked loops
     - TDC-based ADPLL
     - Delay line TDC
     - Delay-locked loops
     - Vernier TDC
     - Cyclic Vernier TDC
     - Digital phase interpolation
     - Digital loop filters (FIR, IIR filters)
     - Digital controlled oscillators (DCOs)
   11) Frequency synthesizers
     - Injection-locked frequency dividers
     - DFF-based frequency dividers
     - Frequency difference detectors
     - Frequency-locking and phase-locking in frequency synthesizers

10-11

Module 7 - Decision feedback equalization (DFE)
   7.1 Decision feedback equalization
       1) Postcursor-induced ISI
       2) Principle of DFE
       3) Configuration of DFE
       4) Characteristics of DFE
       5) Challenges of DFE
       6) DFE blocks

   7.2 Adaptive decision feedback equalization
     1) Classification of DFE
     2) Data-state (DS) DFE
     3) Data-transit (DT) DFE
     4) Weighted DS-DFE and DT-DFE
     5) Adaptive DFE
     6) Least-mean-square (LMS) adaptive DFE algorithm
     7) Sign-sign (S$^2$) LMS adaptive DFE algorithm
     8) SS-LMS implementation
     9) Error detection unit for adaptive DS-DFE
     10) Reference voltages
     11) Error detection unit for adaptive DT-DFE
     12) Charge pumps and loop filters

12-13

Module 8 - Clock and data recovery
    1) Clock recovery
    2) Frequency drift of receiver PLL
    3) Direct coupling and AC coupling
    4) Data encoding
    5) Classification of clock recovery
    6) Clock recovery using phase tracking
    7) Clock recovery using phase picking
    8) Clock recovery using phase interpolation

Laboratory(L)/Tutorials(T)/Activity(A) Schedule

University Policies & Important Information

Week	L/T/A	Description
2/3	Lab 1	Wire channels. Report due : Sunday mid-night of Week 3 if your lab is in Week 2 and Sunday mid-night of Week 4 if your lab is in Week 3.
4/5	Lab 2	Pre-emphasis. Report due : Sunday mid-night of week 5 if your lab is in Week 4 and Sunday mid-night of Week 6 if your lab is in Week 5.
6/7	Lab 3	Continuous-time linear equalizer. CTLE report due : Sunday mid-night of week 7 if your lab is in Week 6 and Sunday mid-night of Week 8 if your lab is in Week 7.
8/9	Lab 4	Phase-locked loop. PLL report due : Sunday mid-night of week 9 if your lab is in Weeks 8 and Sunday mid-night of Week 10 if your lab is in Weeks 9.
10/11	Lab 5	Decision feedback equalizer. Report due : Sunday mid-night of week 11 if your lab is in Week 10 and Sunday mid-night of Week 12 if your lab is in week 11.
12/13	Lab 6	Clock and data recovery. Report due : Sunday mid-night of week 13.

Students are reminded that they are required to adhere to all relevant university policies found in their online course shell in D2L and/or on the Senate website

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Course Outline (W2026)

ELE863: VLSI Circuits for Data Communications