TORONTO METROPOLITAN UNIVERSITY

Course Outline (F2023)

EES508: Digital Systems

Instructor(s)Dr. Nagi Mekhiel [Coordinator]
Office: 446
Phone: (416) 979-5000 x 557251
Email: nmekhiel@torontomu.ca
Office Hours: We 11AM-12PM, TH 9 AM-10 AM
Calendar DescriptionNumber systems, codes and coding, minimization techniques applied to design of logic systems. Component specifications. Discussion of microprocessors, memory and I/O logic elements. Microcomputer structure and operation. I/O modes and interfacing. Machine language and Assembler programming. Design and application of digital systems for data collection and control of pneumatic hydraulic and machine systems. Laboratory work includes the use of microcomputers.
PrerequisitesEES512 and CEN199
Antirequisites

None

Corerequisites

None

Compulsory Text(s):
  1. Brown, S. and Vranesic, Z. Fundamentals of Digital Logic with VHDL Design, Third Edition, McGraw-Hill, 2009 or 4th Ed 2023.
  2. Laboratory Manuals
Reference Text(s):
  1. Hayes, J. Introduction to Digital Logic Design, Addison Wesley, 1993. (Library call number TK7868.L6H29 1993).
  2. Wakerly, J. Digital Design: Principles and Practices, Prentice Hall, 2003. (Library call number TK7874.65.W34 2000).
  3. Dewey, A. Analysis and Design of Digital Systems with VHDL, PWS PublishingCompany, 1997. (Library call number TK7868D5D47 1997).
Learning Objectives (Indicators)  

At the end of this course, the successful student will be able to:

  1. The theoretical and technical knowledge of design methodology from the lecture will be applied in the labs using design tools (Altera® Quartus® II) for analysis, simulation, visualization, synthesis, and design. (4a)
  2. Learning various mathematical models and design methods for digital systems, such as Boolean algebra and optimization design strategies, gives the student the ability to solve principle engineering problems Selects and uses an appropriate method for problem definition. Describes differences between methods, performs a specified method in hypothetical design situation. (4b)
  3. The student has to submit reports for Lab 1 to 5. S/He must read and appropriately responds to technical and non-technical instructions. (7a)

NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB).

Course Organization

4.0 hours of lecture per week for 13 weeks
3.0 hours of lab per week for 12 weeks
0.0 hours of tutorial per week for 12 weeks

Teaching AssistantsTBA
Course Evaluation
Theory
Midterm Exam 30 %
Final Exam 40 %
Laboratory
Lab Work 30 %
TOTAL:100 %

Note: In order for a student to pass a course, a minimum overall course mark of 50% must be obtained. In addition, for courses that have both "Theory and Laboratory" components, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section above for details on the Theory and Laboratory components (if applicable).


ExaminationsMidterm exam in Week 7 or 8, two hours, problems, closed book (covers Weeks 1-7).
 
 Final exam, during exam period, two and half hours, closed-book (covers Weeks 1-13).
 
Other Evaluation InformationNone
Teaching MethodsIn person at the assigned classroom
Other InformationNone

Course Content

Week

Hours

Chapters /
Section

Topic, description

1-2

4

INTRODUCTION TO EES508
 INTRODUCTION TO EES508 and LOGIC CIRCUITS
 (Chapter 2 Sections 2.1 to 2.10)


2-3

4

IMPLEMENTATION TECHNOLOGY
 (Chapter 3 Sections 3.1 to 3.10


3-4

4

OPTIMIZATION OF COMBINATIONAL LOGIC
 (Chapter 4 Sections 4.2 to 4.12)


5-6

4

NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS
 (Chapter 5 Sections 5.1 to 5.8)


6-7

4

COMBINATIONAL CIRCUIT BUILDING BLOCKS
 (Chapter 6 Sections 6.1 to 6.6)


7,8

4

INTRODUCTION TO SEQUENTIAL CIRCUITS
 (Chapter 7 Sections 7.1 to 7.13)


9-10

6

SYNCHRONOUS SEQUENTIAL CIRCUITS
 (Chapter 8 Sections 8.1 to 8.9)


11

3

Register-Level Design, Memory, Interfacing, Input/output
 Hays pp599-605, 609-611, 613


12-13

6

System Architecture
 Processor design including assembly and machine language


Laboratory(L)/Tutorials(T)/Activity(A) Schedule

Week

L/T/A

Description

2-3

TBA

Lab#1  10 marks

4

-TBA

Lab#2 Functional Implementation & Minimization  10 marks

5-6

-TBA

Lab3, Lab4 Adder and Subtractor Unit  15 marks

7-8

-TBA

Lab#5 Combinational Circuits and Storage Elements  15 marks

9-10

-TBA

Lab#6 Sequential Circuits: Implementing an Eight-State Machine 15 marks

11-13

TBA

Simple Processor Module LAB#7 (35 marks)

University Policies

Students are reminded that they are required to adhere to all relevant university policies found in their online course shell in D2L and/or on the Senate website

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