| Instructor(s) | Dr. Nagi Mekhiel [Coordinator] Office: 446 Phone: (416) 979-5000 x 557251 Email: nmekhiel@torontomu.ca Office Hours: We 11AM-12PM, TH 9 AM-10 AM | Calendar Description | This course covers the basics digital logic circuits and emphasizes on good understanding of basic concepts in modern digital system design. The course introduces computer aided design (CAD) tools including the use of hardware description language (HDL) for design entry. It also discusses the use of the latest available implementation technologies including CPLDs and FPGAs for mapping the design to modern technology. This course covers basic logic circuits, Boolean algebra, and implementation technology (from transistor to CPLDs and FPGAs). It also introduces logic functions optimization and implementation, number representation and arithmetic circuits, combinational circuits, synchronous and asynchronous sequential circuits as well as introduction to control unit data path and CPU operations. The Laboratory work requires the uses of CAD tools to design and simulate basic digital circuits. Implementation and testing of simple digital systems in LSI and CPLD will also be considered. | ||||||||||
| Prerequisites | CPS 188, ELE 202, MTH 240 | ||||||||||||
| Antirequisites | None | ||||||||||||
| Corerequisites | None | ||||||||||||
| Compulsory Text(s): |
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| Reference Text(s): |
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| Learning Objectives (Indicators) | At the end of this course, the successful student will be able to:
NOTE:Numbers in parentheses refer to the graduate attributes required by the Canadian Engineering Accreditation Board (CEAB). | ||||||||||||
| Course Organization | 4.0 hours of lecture per week for 13 weeks | ||||||||||||
| Teaching Assistants | TBA | ||||||||||||
| Course Evaluation |
Note: In order for a student to pass a course, a minimum overall course mark of 50% must be obtained. In addition, for courses that have both "Theory and Laboratory" components, the student must pass the Laboratory and Theory portions separately by achieving a minimum of 50% in the combined Laboratory components and 50% in the combined Theory components. Please refer to the "Course Evaluation" section above for details on the Theory and Laboratory components (if applicable). | ||||||||||||
| Examinations | Midterm exam in Week 7 or 8, two hours, closed book (covers Weeks 1-6). Final exam, during exam period, two and half hours, closed-book (covers Weeks 1-13). | ||||||||||||
| Other Evaluation Information | None | ||||||||||||
| Other Information | None | ||||||||||||
Week | Hours | Chapters / | Topic, description |
|---|---|---|---|
1 | 1 | INTRODUCTION TO BME328 | |
1-2 | 4 | INTRODUCTION TO LOGIC CIRCUITS | |
2-3 | 4 | IMPLEMENTATION TECHNOLOGY | |
3-4 | 4 | OPTIMIZATION OF COMBINATIONAL LOGIC | |
4-5 | 4 | NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS | |
5-6 | 4 | COMBINATIONAL CIRCUIT BUILDING BLOCKS | |
6-8 | 8 | INTRODUCTION TO SEQUENTIAL CIRCUITS | |
8-10 | 8 | SYNCHRONOUS SEQUENTIAL CIRCUITS | |
10-11 | 4 | ASYNCHRONOUS SEQUENTIAL CIRCUITS | |
11-12 | 4 | REGISTER-LEVEL DESIGN | |
12-13 | 6 | SYSTEM ARCHITECTURE |
Week | L/T/A | Description |
|---|---|---|
2 | TBA | Lab#1 |
2-3 | TBA | LAB#1 (10 marks) |
4 | TBA | Functional Implementation &Minimization LAB#2 (10 marks) |
5-6 | TBA | Adder and Subtractor Unit LAB#3 and Lab#4 (15 Marks) |
7 | TBA | VHDL for Combinational Circuits and Storage Elements LAB#5 (15 marks) |
8 | TBA | Combinational Circuits and Storage Elements LAB#5 Continue |
9-10 | TBA | Sequential Circuits: Implementing an Eight State Machine LAB#6 (15 marks) |
11-13 | TBA | Simple Processor Module LAB#7 (35 marks) |
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You can submit an Academic Consideration Request when an extenuating circumstance has occurred that has significantly impacted your ability to fulfill an academic requirement. You may always visit the Senate website and select the blue radio button on the top right hand side entitled: Academic Consideration Request (ACR) to submit this request.
For Extenuating Circumstances, Policy 167: Academic Consideration allows for a once per semester ACR request without supporting documentation if the absence is less than 3 days in duration and is not for a final exam/final assessment. Absences more than 3 days in duration and those that involve a final exam/final assessment, require documentation. Students must notify their instructor once a request for academic consideration is submitted. See Senate Policy 167: Academic Consideration.
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