FPGA-accelerated OCT signal processing

2022 COE Engineering Design Project (RP02)

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Faculty Lab Coordinator

Robnier Reyes Perez

Topic Category

FPGAs and Reconfigurable Computing

Preamble

Optical Coherence Tomography (OCT) is a novel imaging modality that allows visualization of vasculature with micrometer resolution. However, this imaging technique requires the processing of large amounts of raw data to form a volumetric image. Due to the high computational demand, real-time OCT imaging is very difficult to obtain. FPGA-accelerated signal processing is a potential solution with which we can obtain video rate speeds for OCT imaging.

Objective

The goal of this project is to increase the speed of the OCT signal processing pipeline with an FPGA-based solution.

Partial Specifications

- The team must perform an literature review to understand the OCT signal processing pipeline and evaluate the advantages and disadvantages between using a Graphical Processing Unit (GPU) and a Field Programmable Gate Array (FPGA)
- The hardware-accelerated signal processing optimization must include cubic interpolation, dispersion compensation, and Fourier transform.
- The hardware-accelerated signal processing frame rate improvement must be compared to a standard solution.
- The team’s solution must be able to accept OCT raw data from a broadband laser and a swept-source laser.

Suggested Approach

- Review how OCT raw data is created and processed to form an image.
- Determine the FPGA with the appropriate number of logic cells, DSP slices, and memory given the processing requirements.
- Determine how data will input the FPGA board from the signal acquisition device or directly from the optical sensor.

Group Responsibilities

All team members are responsible for performing a literature review of the current state of FPGA boards and understand how OCT data is manipulated. This includes but it is not limited to finding peer-reviewed literature, patented solutions, and available solutions. The team is responsible for creating a block level design of the complete system and assigning specific tasks to each of the blocks. Every member is responsible for documenting the design of their subsystem, explaining design choices, and description of the performed tasks.

Student A Responsibilities

This team member will be responsible for determining what computational resources are needed based on the image processing requirements. This student will need to have a strong understanding of image processing techniques. Additional responsibilities as assigned by the FLC.

Student B Responsibilities

The team member will be responsible for writing the hardware description language (HDL) to implement the image processing methods defined by Student A. This student will need to be familiar with HDL languages for different FPGA platform (i.e. Altera, Xilinx). Additional responsibilities as assigned by the FLC.

Student C Responsibilities

The team member will work in close collaboration with Student B and be responsible for writing the hardware description language (HDL) to implement the image processing methods defined by Student A. This student will need to be familiar with HDL languages for different FPGA platform (i.e. Altera, Xilinx). Additional responsibilities as assigned by the FLC.

Student D Responsibilities

This team member will be responsible for display and visualization of the resulting images. Additional responsibilities as assigned by the FLC.

Course Co-requisites

COE328, COE428, COE538

To ALL EDP Students

Due to COVID-19 pandemic, in the event University is not open for in-class/in-lab activities during the Winter term, your EDP topic specifications, requirements, implementations, and assessment methods will be adjusted by your FLCs at their discretion.