SoC Design and Implementation for ECG Analysis

2022 COE Engineering Design Project (GK04)

---

Faculty Lab Coordinator

Gul Khan

Topic Category

FPGAs and Reconfigurable Computing

Preamble

SoPC (FPGA based SoC) have transpired in response to the performance limitations of CPU-based multi-core System-on-Chip (SoC) architectures. SoPC provides dedicated hardware accelerators to improve overall system performance. Electrocardiogram (ECG) records the electrical signal from the heart to check for different heart conditions. ECG application oriented hardware accelerator(s) working along with the CPU will result in a successful high performance SoC implementation for ECG signal analysis.

Objective

Investigate an FPGA based System-on-Programmable Chip (SoPC) to implement ECG Signal Analysis.

Partial Specifications

1. Study typical electrocardiogram (ECG) signals for a human heart to check for different human heart conditions.
2. Investigate and identify a suitable SoPC based on either Intel (Altera) or AMD-Xilinx FPGAs.
3. Investigate ECG signal analysis algorithms/techniques and identify some of its computational intensive parts.
4. Hardware (HDL) implementation of the computational parts of ECG analysis.
5. Implement the rest of ECG analysis algorithm to be executed on the CPU.
6. Hardware-Software implementation using the soft CPU cores and hardware accelerators for the ECG signal analysis application.
7. Verify the working of ECG analysis system for a data-set of typical ECG signals.

Suggested Approach

1. Study and analysis of electrocardiogram (ECG) signals for a human heart.
2. Investigate and evaluate processor architectures and programming models by exploring Intel (Altera) Cyclone IV/V (or AMD-Xilinx) based FPGA platforms for developing the SoC system for ECG signal analysis.
3. CPU (all software) implementation of the ECG analysis technique.
4. HDL (hardware) implementation of computational intensive parts of the ECG analysis method.
5. Hardware-Software design of an SoC involving the CPU (software) and hardware accelerator IPs.
6. Prototyping, implementation and verification (testing) of the SoPC implementation of ECG system by employing some available human ECG Data-sets.

Group Responsibilities

1. Study on-chip ARM processors and programming models as well as FPGA based (Cyclone or Xilinx Zynq SoC) embedded platform for ECG analysis related applications.
2. Investigate and study of ECG techniques being carried out by various groups working on ECG signal analysis.
3. Develop a detailed specification of the ECG analysis technique and its Hardware-software implementation.
4. Design, develop and prototype the ECG analysis technique for the FPGA based SoC platform.
5. Verify the SoC design of an ECG signal analysis technique.
6. Implement a hardware (HDL) accelerator and Software (CPU) implementation of ECG analysis and verify its working for the selected ECG data-sets.

Student A Responsibilities

1. Study some candidate SoPC-based platforms for ECG analysis implementation.
2. Investigate and study of ECG techniques being carried out by various groups working on ECG signal analysis.
3. Identify computational intensive parts of the selected ECG analysis technique and their HDL (hardware) design.
4. Develop a detailed specification of ECG analysis and its Hardware-Software verification in a high level language (such as SystemC).
5. Develop the overall SoPC design for ECG analysis with the collaboration of Students B, C and D.
6. Verify your overall ECG analysis system's design by working with students B, C and D.

Student B Responsibilities

1. Investigate some candidate on-chip ARM processor-based FPGA (SoPC) platforms such a Zynq.
2. Investigate and study ECG analysis techniques being carried out by various groups working on ECG signal analysis.
3. Assist student A to identify computational intensive parts of the selected ECG analysis technique and their HDL (hardware) design.
4. Work with student A to develop a detailed specification of ECG analysis and its Hardware-Software partitioning and verification in co-specification language (such as SystemC or UML).
5. Develop and verify the overall SoPC for ECG analysis with the collaboration of Students A, C and D.
6. Collaborate with students A, C and D to manage the overall project design and implementation.

Student C Responsibilities

1. Identify some candidate on-chip ARM processor-based FPGA (SoPC) platforms.
2. Work with student A and B to develop a detailed specification of the ECG analysis method and its Hardware-Software verification in a high level language (such as SystemC).
3. Support students A and B for the verification and testing the ECG analysis SoC system.
4. Collaborate with students A, B and D to manage the overall project design and implementation.

Student D Responsibilities

1. Study some candidate on-chip ARM processor-based FPGA (SoPC) platforms available for ECG signal analysis.
2. Investigate and study ECG techniques being carried out by various groups working on ECG signal analysis.
3. Assist student A to identify computational intensive parts of the selected ECG analysis technique and their HDL (hardware) design.
4. Design and establish communication in-between CPU (cores) and hardware (HDL) accelerator for the ECG signal analysis application.
5. Develop and verify the overall SoPC for ECG analysis with the collaboration of Students A, B and C.
6. Collaborate with students A, B and C to manage the overall project design and implementation.

Course Co-requisites

COE718, COE838

To ALL EDP Students

Due to COVID-19 pandemic, in the event University is not open for in-class/in-lab activities during the Winter term, your EDP topic specifications, requirements, implementations, and assessment methods will be adjusted by your FLCs at their discretion.