5 .12 Gbps Time-Interleaved Front-End of SerDes

2022 ELE Engineering Design Project (FY06)


Faculty Lab Coordinator

Fei Yuan

Topic Category

Microelectronics

Preamble

High-speed serial data links are the backbone of data-centered applications. To combat the deterioration of signal integrity at high frequencies caused by the finite bandwidth of wire channels, reflection at vias and connectors due to impedance mismatch, and crosstalk with neighboring devices at high frequencies, a number of channel equalization techniques have emerged. Among them, pre-emphasis and post-equalization are proven to be most effective for data rates up to some 30 Gbps per channel. Channel equalization needs to be adaptive so as to combat the detrimental impact of the time-varying characteristics of channels caused by PVT (process, voltage, temperature) uncertainty in an adaptive manner. In addition to channel equalization, clock is transmitted as data transitions and needs to be recovered from equalized data at the receiver, along with the recovery of transmitted data. This capstone design project deals with the design of a 5.12 Gbps (giga-bits-per-second) serial data link transceiver with all-digital adaptive data-state decision feedback equalization and phase-picking clock and data recovery. Incoming data will first be mapped to a set of time variables using time-interleaved voltage-to-time converters. The time variables will then be digitized using flash time-to-digital converters. The digitized incoming data can then be processed using adaptive DFE implemented entirely in the digital domain.

Objective

Design of a 5.12 Gbps time-interleaved front-end of SerDes using a time-based approach

Partial Specifications

1) Data rate: 5.12 Gbps.
2) Near-end pre-emphasis
3) Time-interleaved sample-and-hold, voltage-to-time conversion
3) Clock and data recovery using phase-picking.
4) Technology: TSMC 130 nm 1.2 V CMOS.

Suggested Approach

1) Study the fundamental of serial data communications over wire channels.
2) Develop the architecture of the system.
3) Develop the specifications of the building blocks of the system.
4) Carry out the detailed circuit design of all building blocks of the SerDes and conduct extensive simulation to ensure that the performance of the building blocks meet the design specifications.
5) Simulate the entire transceiver (schematic-level) to ensure that the design specifications are met.
6) Carry out the silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet the design specifications.
7) Conduct the post-layout simulation of the entire design to ensure design specifications are met.

Group Responsibilities

The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.

Student A Responsibilities

Serializer, pre-emphasis block, current-mode driver.

Student B Responsibilities

Continuous-time linear equalizer, sample-and-hold, voltage-to-time converter

Student C Responsibilities

Digitally controlled oscillator, samplers, time-to-digital converters.

Student D Responsibilities

Frequency synthesizer (phase-frequency detector, time-to-digital converter, digital loop filter, and frequency dividers) that generates a 2.56 GHz clock from a 10 MHz reference clock. The frequency synthesizer is to be used by both the transmitter and receiver.

Course Co-requisites

ELE724 or ELE727 or ELE 863

To ALL EDP Students

Due to COVID-19 pandemic, in the event University is not open for in-class/in-lab activities during the Winter term, your EDP topic specifications, requirements, implementations, and assessment methods will be adjusted by your FLCs at their discretion.

 


FY06: 5 .12 Gbps Time-Interleaved Front-End of SerDes | Fei Yuan | Friday September 2nd 2022 at 10:26 AM