Successive Approximation Analog-to-Digital Converter with Time-Mode Comparator

2022 ELE Engineering Design Project (FY05)

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Faculty Lab Coordinator

Fei Yuan

Topic Category

Microelectronics

Preamble

Analog-to-Digital Converters (ADCs) play an important role from biomedical sensors to cellular phones. Among various architectures of ADCs, successive approximation register (SAR) ADCs introduced in 1950s and debuted in CMOS in 1970s played a major role in advancing the state-of-the-art of ADCs since their inception. Although popular in telephony and instrumentation where data rate is typically low in the past, SAR ADCs have re-established themselves as the most promising ADC architecture inherently crafted for modern CMOS technologies with emerging applications in wireless sensors and biomedical instruments where power consumption is of a great importance The power consumption of SAR ADCs rises sharply with their resolution, mainly due to the increased transconductance of the front-end transistors of comparators needed to sense and amplify a very small voltage. As a result, the resolution of voltage-mode SAR ADCs is limited to approximately 10 bits. One attractive technique emerged recently is time-based comparators that are capable of detecting a very small input voltage without power-consuming voltage-mode comparators. This capstone design project develops a 10-bit SAR ADC with a time-time comparator.

Objective

This capstone design project develops a 10-bit SAR ADC with a time-time comparator.

Partial Specifications

1) SAR ADC with a time-mode comparator for low power.
2) Full-range-scale of input: 400 mV
3) Data rate: 100 kS/s.
4) ENOB (Effective number of bits): 10.
5) Technology: TSMC 130 nm 1.2V CMOS.

Suggested Approach

1) Study the fundamental of ADCs and SAR ADCs.
2) Study the fundamental of time-based signal processing.
3) Develop the architecture of the system and the specifications of the building blocks of the system.
4) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
5) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet design specifications.
6) Carry out the post-layout simulation of the entire ADC to ensure that the performance of the building blocks meet the design specifications.

Group Responsibilities

The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.

Student A Responsibilities

The student is responsible for the design and implementation (schematic and layout) of a voltage-to-time converter that maps a pair of differential voltages to a time variable and the sample-and-hold (S/H) block of the SAR ADC with bootstrapped switches.

Student B Responsibilities

The student is responsible the design and implementation (schematic and layout) of a 10-bit SAR using top-plate sampling, a differential capacitive DAC including the switching network, and SAR.

Student C Responsibilities

The student is responsible the design and implementation (schematic and layout) of both the voltage-mode comparator and the time-based comparator. In upper 8 MSB conversions, the voltage-mode comparator should be used whereas in lower 2 LSB conversion, the time-mode comparator should be used. Logic that implements the above comparator selection should be developed.

Student D Responsibilities

The student is responsible the design and implementation (schematic and layout) of the clock for S/H, SAR, and comparator. The clock is generated using a delay-locked loop that locks to a reference clock of 100 kHz.

Course Co-requisites

(ELE 724 or ELE 727) and ELE 827 (at least two students should take ELE 827)

To ALL EDP Students

Due to COVID-19 pandemic, in the event University is not open for in-class/in-lab activities during the Winter term, your EDP topic specifications, requirements, implementations, and assessment methods will be adjusted by your FLCs at their discretion.