Successive Approximation ADC with Time-Mode Noise-Shaping

2022 ELE Engineering Design Project (FY04)

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Faculty Lab Coordinator

Fei Yuan

Topic Category

Consumer Products/Applications

Preamble

Analog-to-Digital Converters (ADCs) play an important role in from biomedical sensors to cellular phones. Among various architectures of ADCs, successive approximation register (SAR) ADCs introduced in 1950s and debuted in CMOS in 1970s played a major role in advancing the state-of-the-art of ADCs since their inception. Although popular in telephony and instrumentation where data rate is typically low in the past, SAR ADCs have re-established themselves as the most promising ADC architecture inherently crafted for modern CMOS technologies with emerging applications in wireless sensors and biomedical instruments where power consumption is of a great importance. The power consumption of SAR ADCs rises sharply with their resolution mainly due to the increased transconductance of the front-end transistors of comparators needed to sense and amplify a very small voltage. As a result, the resolution of voltage-mode SAR ADCs is limited to approximately 10 bits. One attractive technique emerged recently is the addition of noise-shaping capability to further digitize the residual voltage of the SAR ADC so as to achieve an improved resolution. Noise-shaping is realized using a time-mode delta-sigma modulator whose input is the time variable mapped from the residual voltage of the SAR ADC. This capstone design project develops a SAR ADC with time-mode noise-shaping.

Objective

This capstone design project develops a SAR ADC with time-mode noise-shaping.

Partial Specifications

1) SAR ADC with first-order time-mode noise-shaping
2) Full-scale-range of input: 400 mV
3) Data rate: 100 kS/s.
4) ENOB (Effective number of bits): 10.
5) Technology: TSMC 130 nm 1.2V CMOS.

Suggested Approach

1) Study the fundamental of ADCs, SAR ADCs, and delta-sigma modulators.
2) Develop the architecture of the system and the specifications of the building blocks of the system.
3) Carry out detailed circuit design of all building blocks and conduct extensive simulation to ensure that the performance of the building blocks meet design specifications.
4) Carry out silicon implementation of the building blocks and conduct post-layout simulation to ensure that the performance of the building blocks meet design specifications.
5) Carry out the post-layout simulation of the entire ADC to ensure that the performance of the building blocks meet the design specifications.

Group Responsibilities

The group members of the project will work as a team to undertake this challenging project. A full corporation is needed to ensure the progress and completion of the project.

Student A Responsibilities

The student is responsible for the design and implementation (schematic and layout) of a voltage-to-time converter that maps a pair of differential voltages to a time variable and the sample-and-hold (S/H) block of the SAR ADC.

Student B Responsibilities

The student is responsible the design and implementation (schematic and layout) of an 8-bit SAR with top-plate sampling, a differential capacitive DAC including the switching network, and comparator.

Student C Responsibilities

The student is responsible the design and implementation (schematic and layout) of a voltage-to-time converter that maps the residual voltages of the SAR ADC to a time variable. The student is also responsible for the generation of the for S/H and SAR. The clock is generated using a delay-locked loop that locks to a reference frequency of 100 kHz.

Student D Responsibilities

The student is responsible the design and implementation (schematic and layout) of the time integrator using a bi-directional gated ring oscillator (BDGRO) and the bi-directional shift register (BDSR) that functions as an up-down counter. In addition, the student is responsible for the design of time summer that generates the time error signal to be integrated by the time integrator.

Course Co-requisites

(ELE 724 or ELE 727) and ELE 827 (at least two students should take ELE 827)

To ALL EDP Students

Due to COVID-19 pandemic, in the event University is not open for in-class/in-lab activities during the Winter term, your EDP topic specifications, requirements, implementations, and assessment methods will be adjusted by your FLCs at their discretion.