HDL Implementation of SATA I/O Protocol for an Embedded System

2019 COE Engineering Design Project (GK06)

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Faculty Lab Coordinator

Gul Khan

Topic Category

Embedded Systems

Preamble

Expansion of an existing ARM CPU based board by including some sophisticated hardware functionality required for a computational platform is requied. One of such expansion can be in terms of an I/O controller for storage. SATA protocol is useful to interface storage devices in the form of Hard drives or SSDs. A SATA interface constitute a complete capstone design project, where the capstone design group is to choose a basic version of SATA protocols for implementation, and design it by using Verilog or VHDL to complete a HDL IP of a SATA controller. The design will be tested and verified using System-Verilog from the module to the system level. The designed HDL is to be prototyped on the FPGA. The prototype is to be demonstrated through basic communication with a storage device for such as hard disk.

Objective

HDL (Verilog or VHDL) design and implementation of SATA protocol for ARM Cortex CPU accommodated development board.

Partial Specifications

1. Study the basic SATA interface and its protocol for embedded system implementation.
2. Use Verilog or VHDL for hardware implementation of the SATA protocol.
3. Synthesis of the HDL design of the SATA protocol and implement it for the target FPGA-based board.
4. Identify a SATA device to be interfaced with your SATA interface IP design.
5. Verify the newly designed SATA by interfacing it to a SATA based Hard disk.

Suggested Approach

1. Study various SATA protocols and select the basic SATA protocol for implementation.
2. Study and select various embedded platforms for SATA controller implementation.
3. Study Verilog for RTL (hardware) design of the SATA protocol.
4. Design and Implement (preferably Verilog based) the RTL of basic SATA protocol.
5. Synthesize your Verilog RTL design of the SATA protocol and implement it on the embedded platform.
6. Verify the SATA protocol HDL design.
7. Interface a storage (e.g. hard-disk) via the implemented SATA protocol.

Group Responsibilities

1. Investigate and study various I/O and SATA protocols.
2. Study various platforms for SATA implementation and select a suitable FPGA-based board/platform.
4. Study Verilog or VHDL for RTL (hardware) design of the SATA I/O protocol.
5. Design and Implement (preferably Verilog-based) the RTL of the SATA protocol.
6. Synthesize the RTL/HDL design of the protocol and implement it on the target platform.
7. For verification, interface a SATA hard-disk via the implemented SATA protocol with the FPGA-based embedded board.

Student A Responsibilities

1. Investigate various I/O protocols including SATA and some similar protocols.
2. Study a couple of suitable FPGA-based embedded platform (having an ARM Cortex CPU) for the SATA protocol implementation.
3. Study Verilog or VHDL for HDL design of SATA protocol.
4. Develop part-1 of the RTL hardware design of SATA using Verilog or VHDL.
5. Develop and synthesize the SATA protocol (HDL) design by working with Student B and C for the target platform.
6. Assist Student B, C and D and manage the overall design and implementation.

Student B Responsibilities

1. Study various SATA protocols for design and implementation.
2. Study suitable FPGA-based embedded platforms (having an ARM Cortex CPU) and identify one for SATA protocol implementation.
3. Study Verilog or VHDL for HDL design of SATA protocol.
4. Develop part-2 of the RTL hardware design of SATA using Verilog or VHDL.
5. Develop and synthesize the PCI-E protocol (RTL) design by working with Student A and C for the target platform.
6. Assist Student A, C and D and manage the overall project design and implementation.

Student C Responsibilities

1. Study various SATA protocols for design and implementation.
2. Identify a suitable FPGA-based embedded platforms (having an ARM Cortex CPU) for PCI-E protocol implementation.
3. Study Verilog or VHDL for HDL design of SATA protocol.
4. Develop part-3 of the RTL hardware design of the protocol using Verilog or VHDL.
5. Develop and synthesize the SATA protocol (RTL) design by working with Student A and B for the target platform.
6. Assist Student A, B and D and manage the overall project design and implementation.

Student D Responsibilities

1. Investigate some candidate embedded boards and/or platforms with FPGA for SATA implementation.
2. Study the SATA protocol for HDL implementation.
3. Study and learn Verilog or VHDL for RTL (hardware) design of the SATA protocol.
4. Participate in the RTL design of the protocol using Verilog or VHDL.
5. For verification, interface a SATA hard disk via the implemented protocol with the FPGA board with the help of other students.
6. Assist Student A, B and C to manage the overall project and implementation.

Course Co-requisites

COE718, COE838